FIG. 4 is a flowchart showing a case where arithmetic target data are subjected to a processing which differs according to whether the arithmetic target data satisfies a certain condition or not as for, for example whether the arithmetic target data is zero, with using a data processor including a general-purpose instruction set, such as a microprocessor and a DSP, or a semiconductor integrated circuit apparatus which is called a system LSI in which such a data processor is mounted.
In this FIG. 4, initially in step S401, an arithmetic target data 402 is obtained. Then, in step S403, a process for comparing the data 402 which has been obtained in the previous step S401 with zero is carried out to confirm that the data 402 is zero or not.
In the subsequent step S404, upon receipt of the result of the previous step S403, when the comparison result shows noncoincidence (No), the operation proceeds to step S406 to carry out a process B. On the other hand, when the decision result in step S404 shows coincidence (Yes), the arithmetic target data 402 is subjected to a process A in step S405, and thereafter the operation proceeds to step S406.
Here, assume that the process B is a process using the arithmetic target data, or a data which is obtained by subjecting the arithmetic target data to the arithmetic of the process A.
As described above, in the flowchart of FIG. 4, according to the execution result of step S404, the following processing procedure, i.e., the flow of data processing differs.
One of the instructions which are included as the general-purpose instruction set in the common processors which are called microprocessors, DSPs or the like is a conditional branch instruction. According to the conditional branch instruction, a code which is called a condition code having information which indicates the property of an arithmetic result is previously generated and retained in an arithmetic instruction to be executed, and when this condition code coincides with a condition which is specified by the conditional branch instruction, the condition is decided to be satisfied and branching is executed, and when this code does not coincide with the condition, the condition is decided not to be satisfied, and branching is not executed. Therefore, a conditional branch instruction is commonly used for executing the process for causing the branch of the processing flow after the condition decision as in step S404 in the flowchart of FIG. 4.
Although the conditional branch instruction which is required in a case where the processing as shown in FIG. 4 is carried out has an operation which does not directly contribute the data processing, it should be described by if-then-else statements or the like. However, in this method, the execution of a micro code which processes an if statement corresponding to one conditional branch requires several execution cycles, and this should be repeated by the number of data. Further, in a system LSI in which a pipeline control is exerted on a program, the flow of pipeline is interrupted, resulting in an increased overhead of the processing.
In order to prevent such a reduction in the processing performance, there are some models including an instruction which is called a conditional arithmetic instruction in the instruction set. According to this conditional arithmetic instruction, a similar condition to that of the branch instruction is added to various instructions, then only when the specified condition is satisfied, this instruction is executed, and when this condition is not satisfied, the operation directly proceeds to the next step without executing the specified operation. When this instruction is included, the conditional branch instruction as in step S404 of FIG. 4 can be excluded from the program, whereby the reduction in the processing performance can be avoided.
When this conditional arithmetic is to be performed to a large amount of data, it is previously operated whether each of the data satisfies the condition or not, the result is retained separately in a mask register as a flag, and then it is decided whether the arithmetic is to be performed or not with referrinq to this flag. However, this flag computing as the preprocessing incurs the overhead, and further the mask register for retaining this flag is separately required.
Further, as an improved one including this type of conditional arithmetic instructions, Japanese Published Patent Application No. Hei. 08-305563 discloses a data processor in which a small number of bits are added to arithmetic instruction data to select whether the arithmetic instruction is executed without reservation, when a condition is “true”, or when the condition is “false”, thereby avoiding a reduction in the performance according to types of the conditional arithmetic instruction or due to restrictions on flexibility in operands, whereby the capacity of a program memory can be reduced.
When a large amount of data such as image data are to be subjected to the processing in which when an arithmetic target data is zero “1” is added to the arithmetic target data in the process A, and when the arithmetic target data is not zero the operation proceeds directly to the next process, this situation should be coped with by the prior art arithmetic method or arithmetic unit by using either the method of describing the flow shown in FIG. 4 by the micro codes corresponding to the if-then-else statements or the like to repeat this the number-of-data times, or the method of repeating a flow which is obtained by excluding step S404 from the flow the number-of-data times with using the conditional arithmetic instruction. However, in these methods, the instruction cannot be subjected to the vector arithmetic process, and accordingly the repeat processing which is repeated the number-of-data times using a loop is required, thereby increasing the overhead in the processing.
Usually, there may be few programs in which processing modules which perform the above-mentioned conditional arithmetic frequently appear. However, in a processing module like a image CODEC signal processing, a prescribed processing routine is often executed repeatedly for enormous amounts of data, and when the number of steps included in the processing routine is increased or decreased even by one step, the processing performance is greatly affected.
The present invention is made in view of the above-mentioned circumstances, and its object is to provide a conditional vector arithmetic method and a conditional vector arithmetic unit, which can subject conditional arithmetic to a vector arithmetic process when a processing by a processing routine including the above-mentioned conditional arithmetic is carried out for a large amount of data, requires no separate mask register, reduces the overhead in a processing which is required for a repeat processing, and increases the processing performance.